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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
Figure 73: WRITE to Power-Down Entry
BL = 4
T0
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
CK#
CK
WL
CKE 1
BL/2
t WR
t ISCKE
CMD
WRITE
DQ
D IN
D IN
D IN
D IN
DQS#
DQS
BL = 8
T0
T1
Tm
Tm +m1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK#
CK
WL
BL/2
t ISCKE
CKE 1
t WR
CMD
WRITE
DQ
D IN
D IN
D IN
D IN
D IN
D IN
D IN
D IN
DQS#
DQS
Note:
1. CKE can be registered LOW at (WL + 1 + BL/2 + RU( t WR/ t CK)) clock cycles after the clock
on which the WRITE command is registered.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
98
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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